1. Field of the Invention
The present invention relates to a data input and output control apparatus for a video memory, and particularly to an apparatus for controlling a first-in-first-out (FIFO) memory capable of simultaneously performing write/read operations of video data with respect to the FIFO memory.
2. Description of Related Art
Generally, video processing equipment for use in a closed-circuit television (CCTV) such as a frame switcher, a sequential switcher and a quad unit, uses a FIFO memory and synchronizes an asynchronous video signal. Here, the FIFO memory perfoms a function of a buffer, to thereby store encoded and irregularly input video data and transmit the stored video data at a constant velocity. Accordingly, an overflow or underflow phenomenon does not occur. On the other hand, the FIFO memory used at the receiving ends stores the video data which is transmitted at a constant velocity and outputs the stored video data in response to a predetermined bit so as to be decoded when there is a request for reading. In these cases, a circuit for controlling a read/write operation of the FIFO memory by using control signals in connection with the video data which is currently input to the FIFO memory is required.
FIG. 1 is a schematic block diagram of a conventional circuit for controlling a write operation in a FIFO memory. The FIG. 1 control circuit 10 receives control signals HD, VD, FLDS, OE and CLEAR which relate to the video data currently input to the FIFO memory, and generates a write enable signal WE which is used for writing a video signal constituting a single video frame with two fields in the FIFO memory (not shown). These control signals are synchronized with the system clock, in which HD is a horizontal sync signal for controlling a write system, VD is a vertical sync signal for controlling the write system, FLDS is an odd/even field flag signal for controlling a read system, OE is an odd/even field flag signal for controlling the write system and CLEAR is a signal for clearing control circuit 10. FLDS and OE are signals for discriminating if the input video data is an odd field or an even field, respectively. When control circuit 10 generates write enable signal WE based on input control signals HD, VD, FLDS, OE and CLEAR, and applies the generated write enable signal WE to the FIFO memory, input data is written in the FIFO memory according to a state of a level of write enable signal WE.
However, when the video data is read according to the features of the FIFO memory, such a conventional apparatus may not determine whether the previously written video data should be read or the newly written video data should be read. In this case, a video data mixture of the previously written data with the newly written data is output from the FIFO memory. Thus, when such video data is displayed on a screen, an abnormal picture may be regenerated thereon.